====== x86-64 Page Table ======

PGD:

<code>
Bits 63:    NX (no-execute) — not used at PGD level typically
Bits 62-52: Available for OS use
Bits 51-12: Physical address of the PUD page (shifted right, page-aligned), 40 bits
Bits 11-9:  Available for OS use  
Bit  8:     Global
Bit  7:     PS (page size) — if set, this is a huge page leaf
Bit  6:     Dirty
Bit  5:     Accessed
Bit  4:     PCD (cache disable)
Bit  3:     PWT (page write-through)
Bit  2:     U/S (user/supervisor)
Bit  1:     R/W (read/write)
Bit  0:     P (present)
</code>

PUD:

<code>
Bit 63:    NX  - No Execute (requires EFER.NXE=1)
Bits 62-52: Available for OS use (e.g. swap info when not present)
Bits 51-30: Physical address of PMD page (bits 51:30, 1GB aligned if PS=1)
            OR physical address of PUD page table if PS=0, 22 bits
Bits 29-13: Available (when PS=1 huge page, these are ignored/reserved)
Bit 12:    PAT - Page Attribute Table index bit 2 (only when PS=1)
Bit 11-9:  Available for OS use
Bit 8:     G   - Global (don't flush from TLB on CR3 switch)
Bit 7:     PS  - Page Size: 0=points to PMD table, 1=1GB huge page leaf
Bit 6:     D   - Dirty (set by CPU on write, only meaningful if PS=1)
Bit 5:     A   - Accessed (set by CPU on any access)
Bit 4:     PCD - Page Cache Disable
Bit 3:     PWT - Page Write Through
Bit 2:     U/S - User/Supervisor: 0=kernel only, 1=user accessible
Bit 1:     R/W - Read/Write: 0=read only, 1=writable
Bit 0:     P   - Present: 0=not mapped (rest of bits free for SW use)
</code>

PMD:

<code>
Bit 63:    NX  - No Execute
Bits 62-52: Available for OS use
Bits 51-21: Physical address of PTE page (bits 51:21, 2MB aligned if PS=1), 31 bits
Bits 20-13: Reserved/ignored (when PS=1)
Bit 12:    PAT - Page Attribute Table index bit 2 (only when PS=1)
Bits 11-9:  Available for OS use
Bit 8:     G   - Global
Bit 7:     PS  - Page Size: 0=points to PTE table, 1=2MB huge page leaf
Bit 6:     D   - Dirty
Bit 5:     A   - Accessed
Bit 4:     PCD - Page Cache Disable
Bit 3:     PWT - Page Write Through
Bit 2:     U/S - User/Supervisor
Bit 1:     R/W - Read/Write
Bit 0:     P   - Present
</code>

PTE:

<code>
Bit 63:    NX  - No Execute
Bits 62-52: Available for OS use
Bits 51-12: Physical address of 4KB page (bits 51:12), 40 bits
Bits 11-9:  Available for OS use (Linux uses for soft-dirty, uffd, etc)
Bit 8:     G   - Global
Bit 7:     PAT - Page Attribute Table index bit 2
Bit 6:     D   - Dirty (set by CPU on write)
Bit 5:     A   - Accessed (set by CPU on read or write)
Bit 4:     PCD - Page Cache Disable
Bit 3:     PWT - Page Write Through
Bit 2:     U/S - User/Supervisor
Bit 1:     R/W - Read/Write
Bit 0:     P   - Present
</code>